1. Technical Field
Example embodiments relate to a resistive random access memory (RRAM) and a method of manufacturing the RRAM.
2. Description of the Related Art
A semiconductor memory array structure may include a plurality of interconnected memory cells. For example, a unit memory cell of a dynamic random access memory (DRAM) may include a switch and a capacitor. A DRAM may have higher integration and faster operating speeds. However, when the power is turned off, all of the stored data may be erased from the DRAM.
On the other hand, a flash memory may be representative of a non-volatile memory capable of preserving stored data when the power is turned off (unlike a volatile memory) but may have lower integration and slower operating speeds than a DRAM. Examples of a non-volatile memory may include a magnetic RAM (MRAM), a ferroelectric RAM (FRAM), and a phase-change RAM (PRAM). A MRAM may store data using a change in the polarization direction of a tunnel junction. A FRAM may store data using the polarization characteristic of a ferroelectric. The MRAM and the FRAM may have higher integrations, faster operating speeds, and improved data retention characteristics and may be driven at a lower power. A PRAM may store data using a change in a resistance value depending on the phase change of a specific material and may include a resistor and a switch (transistor). However, where a conventional DRAM process is used to manufacture the PRAM, etching may be more difficult and may require a longer period of time. Thus, productivity may be lowered, and the unit cost of products may be increased. Consequently, market competitiveness may be decreased.
A resistive RAM (RRAM) may store data using the variable resistance characteristic (e.g., a resistance value varying with voltage) of a transition metal oxide. FIG. 1A is a cross-sectional view of a conventional RRAM using a resistive transformation material. Referring to FIG. 1A, the conventional memory device may include a resistive layer 12 and an upper electrode 13 sequentially formed on a lower electrode 11. The resistive layer 12 may be formed of a transition metal oxide, and the lower and upper electrodes 11 and 13 may be formed of a conductive material, e.g., a metal or a metal oxide.
FIG. 1B is a graph illustrating a relationship between a voltage applied through the lower and upper electrodes 11 and 13 and a current flowing in the resistive layer 12 of the conventional RRAM of FIG. 1A. The voltage may be gradually increased from 0 V to measure variations in the current flowing in the resistive layer 12. The current flowing in the resistive layer 12 may be gradually increased at an applied voltage between about 0 V and about 1 V. The current may decrease with an increase in resistance at a voltage of about 1 V and may increase again with a further increase in voltage. A higher resistance state may refer to a reset state, and a lower resistance state may refer to a set state. Variations in the intensity of a voltage at which the set state is changed into the reset state (e.g., a reset voltage RV) and variations in the intensity of a set resistance SR may be relatively large. Also, the set voltage SV at which the reset state is changed into the set state may have a relatively large variation.
FIGS. 2A through 2C illustrate a current path formed in the resistive layer 12 because of a voltage applied through the lower and upper electrodes 11 and 13 of the conventional RRAM. Referring to FIG. 2A, when a voltage is applied through the lower and upper electrodes 11 and 13, a current may flow in the resistive layer 12. Poles formed on a flat board of FIG. 2A may denote the current path. Referring to FIG. 2B, a current path may not be formed in an off state where voltage is not applied. Referring to FIG. 2C, when a voltage is applied through the lower and upper electrodes 11 and 13, a current may flow in the resistive layer 12. The current path of FIG. 2A may be different from the current path of FIG. 2C. For example, while the current may flow in a circular area of FIG. 2A, the current path does not appear to flow in a circular area of FIG. 2C. Thus, a current path formed in the resistive layer 12 may vary with the application of voltage. Accordingly, voltage and resistance variations, as shown in FIG. 1B, may occur.
Because the current path in the resistive layer 12 may not be uniform with the driving of the conventional RRAM (and thus the resistance level may be relatively unstable), the conventional RRAM may have larger voltage and resistance variations. Consequently, the set and reset voltages of the conventional RRAM may be relatively unstable, thus lowering reliability.